With the advance of technology in integrated circuits (ICs), the minimum feature sizes of ICs have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography. Photolithography involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers (e.g., regions of substrate, polysilicon, or dielectric).
An integral component of a photolithographic apparatus is a “reticle” or “mask” which includes a pattern corresponding to features at one layer in an IC design. Such a mask may typically include a transparent glass plate covered with a patterned light blocking material such as chromium. The mask may be placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper may be a resist covered silicon wafer. When the radiation from the radiation source is directed onto the mask, light may pass through the glass (regions not having chromium patterns) and project onto the resist covered silicon wafer. In this manner, an image of the mask may be transferred to the resist. The resist (sometimes referred to as a “photoresist”) is provided as a thin layer of radiation-sensitive material that is spin-coated over the entire silicon wafer surface.
As light passes through the mask, the light may be refracted and scattered by the chromium edges. This may cause the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), the effects may not be ignored in layouts having features smaller than about 1 micron. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process. Optical distortions commonly encountered in photolithography may include rounded corners, reduced feature widths, fusion of dense features, shifting of line segment positions, and the like. Unfortunately, any distorted illumination pattern may propagate to a developed resist pattern and ultimately to IC features such as polysilicon gate regions, vias in dielectrics, and the like. As a result, the IC performance may be degraded or the IC may become unusable.
To remedy this problem, a mask correction technique known as optical proximity correction (“OPC”) has been developed. OPC may involve adding regions to and/or subtracting regions from a mask design at locations chosen to overcome the distorting effects of diffraction and scattering. Manual OPC has been in existence for many years. Using manual OPC, an engineer may need to add regions using trial and error techniques until the desired pattern on the wafer is obtained. While manual OPC has been effective, as the dimensions of critical features shrink, it has become apparent that the manual approach is not time/cost effective. Therefore, a systematic way is needed to enable fast processing of large, complex chips. Generally speaking, there are currently two automated approaches to OPC: (1) rule-based OPC (use geometric rules to add corrections); and (2) model-based OPC (use lithography simulations to decide corrections). Rule-based OPC is an extension of the methods used for manual OPC. Through experiment or simulation, the corrections that should be applied in a given geometrical situation may be discovered. Then, a pattern recognition system may be used to apply the corrections wherever that geometrical situation occurs throughout the entire layout design. While rule-based OPC is fast and can be applied to an entire layout, rule-based OPC is not as accurate as desired because rule-based OPC is not directly based on lithography simulation. Model-based OPC is different from rule-based OPC in that simulation models are used to compute the wafer results and modify edges on the mask to improve the simulated wafer results. Model-based OPC may be capable of more general corrections, but may require longer OPC time since simulation is typically time-intensive. The use of lithography simulation has been traditionally for analysis of aerial images and cutlines. The aerial image has long been used as a first order approximation to the final etched features produced by photolithography. Presently the role of lithography simulation has been broadened to include use of simulation within mask design synthesis tools.
A high density chip design is a chip design that has a distance of less than 0.8λ among input design boundaries, where λ is the wavelength of the light source. Model-based OPC of such a design often leads to a chip design with even higher density, because the movement of fragmentation regions of the edge (edge correction) may be essential (typically in the range of 0.3–0.4λ). The light intensity (or intensity) information alone may be not enough for the OPC of a high density chip design, since for such a design there is no single-value conformity between the edge corrector value change and the position of the process light intensity contour relative to the mask edge. The intensity value at a certain point may depend on the set of edge correctors at the influence region surrounding this point. Thus, the movement of all these correctors need be coordinated.
Therefore, it would be desirable to provide a method and apparatus for making mask edge corrections using a gradient method for high density chip designs.